1. Field of the Invention
The present invention is generally concerned with a device for slaving the frequency of a local clock signal to N times the frequency of a master clock signal where N is a predetermined integer.
2. Description of the Prior Art
Such a local clock signal frequency slaving device is typically used during a frequency maintaining phase following on from a frequency acquisition phase. The frequency of the local clock signal equal to N times the frequency of the master clock signal is acquired during the acquisition phase and this acquired frequency is maintained by the frequency slaving device.
The invention finds one application in the field of telecommunications for slaving the frequency of a sampling local clock signal in a receiving system to N times the frequency of a master clock signal received by the system. The frequency of the master clock signal is, for example, the frequency of data frames received by the receiving system. In this example, the local clock signal has a frequency equal to the frequency of the binary elements in each frame, N being then equal to the number of bits in a frame. A such application example of the invention can recover the frequency of the binary elements in each frame from the frame frequency in order to sample the binary elements and so recover the data included in the frames.
FIG. 1 is a block diagram of a prior art frequency slaving apparatus or device 1, also called as a frequency control device, with which the person skilled in the art is very familiar. The device 1 is a phase-locked loop comprising a phase comparator 10, a filter 11, a voltage controlled oscillator 12 and a divide-by-N frequency divider 13. The comparator 10, the filter 11 and the oscillator 12 are connected in cascade in that order. An output of the oscillator 12 is fed back to a first input 10.sub.1 of the phase comparator 10 through the frequency divider 13. A second input 10.sub.2 of the phase comparator 10 receives a master clock signal Sp at a master frequency fp.
The frequency slaving device shown in FIG. 1 operates as follows:
The phase comparator 10 compares the phase of the master clock signal Sp with the phase of a slaving clock signal Sa produced from the output of the frequency divider 13 and supplies a control voltage Vc to control the oscillator 12 via the filter 11. The slaving clock signal Sa has a frequency fa which is N times smaller than the frequency fl of the local clock signal S1 at the output of the oscillator 12 and substantially equal to the frequency fp of the master clock signal Sp.
The prior art device 1 is typically used when the frequency ratio fl/fp between the frequency fl of the local clock signal S1 and the frequency fp of the master clock signal Sp is less than a value substantially equal to 10.sup.4. It is to be noticed that if the frequency fp of the clock signal Sp is very low, i.e., if the period of the signal Sp is very high, the device 1 cannot be used because of manufacturing problems with the filter 11, as its components must have high values to filter the control signal Vc and also to ensure an accurate control of the oscillator 12.
If the frequency ratio fl/fp is greater than a value substantially equal to 10.sup.4 the device 1 cannot be used. An infinitesimal increase or decrease in the frequency fl of the signal S1 produced by the oscillator causes only a very small variation in the phase of the control clock signal Sa, given the ratio of the periods of the signals Sa and S1, with the result that the device is inaccurate.
In practice, when the frequency ratio fl/fp is high, typically greater than 104, the prior art technique uses two frequency slaving devices 1 and 2 of the type shown in FIG. 1 connected in cascade. In this implementation shown in block diagram form in FIG. 2, each of the first and second frequency slaving devices is a phase-locked loop comprising a phase comparator 10, 20, a filter 11, 21, a voltage controlled oscillator 12, 22 and a frequency divider 13P, 23 arranged in the same manner as in FIG. 1. The output of the oscillator 12 in the first slaving device 1 is applied to a second input 20.sub.2 2 of the phase comparator 20 in the second slaving device 2. The two frequency slaving devices 1 and 2 connected in cascade yield a frequency multiplication factor equal to N=(P.times.M) corresponding to the multiplication of two frequency division ratios P and M in the frequency dividers 13P and 23. The second oscillator 22 produces a local clock signal S1 having a frequency N=(P.times.M) times greater than the frequency fp of the master clock signal Sp applied to the second input 10.sub.2 of the phase comparator 10.
This implementation solves the problem previously stated relating to an excessively high multiplication ratio between the frequency fp of a master clock signal Sp received and the frequency fl of a local clock signal S1 to be generated.
However, both prior art implementations have the following drawbacks.
For applications in which the frequency ratio between the frequency fl of the local clock signal S1 and the frequency fp of the master clock signal fp is very high, typically greater than 10.sup.4, the device 1 cannot be used. The FIG. 2 implementation doubles the number of electronic components as two phase locked loops are used and thus increases the cost.